One of the challenges facing the users and designers of integrated circuits is managing the power produced by a chip. The power dissipated by a digital chip has two basic sources which are switching current and leakage current. When a gate is switching from one logical value to another, there is a brief period time where current passes through the transistors dissipating power in the form of heat. Historically, this switching current has been the focus of the designer's attention because it was substantially greater than the nominal leakage current that occurred when the gate was not switching and the transistors were “off”.
However, with smaller geometries and reduced operating voltages, the leakage current is a significantly larger proportion of the power production problem. Thus, chip designers need to develop both on and off chip techniques for dealing with leakage current. One of the challenges is accurately measuring the amount of leakage current that is actually present on a particular chip.